The present invention relates generally to transistor devices, and in particular a complementary bipolar SRAM, and a method of building and operating a complementary bipolar SRAM.
Semiconductor-on-Insulator (SOI) lateral bipolar transistors are ideally suitable for building complementary bipolar inverters, which is the basic building block for complementary bipolar circuits. The teaching of a complementary lateral bipolar inverter using SOI can be found in U.S. Pat. No. 8,531,001.
FIG. 1 shows a SOI lateral bipolar inverter device 10 according to prior art implementations. In FIG. 1 the SOI lateral bipolar junction transistor (BJT) device 10 includes a first bipolar (P-N-P) transistor 12 and a second bipolar (N-P-N) transistor 15 formed on an SOI substrate 11. In the device 10, the base terminal of the PNP bipolar junction transistor 12 is electrically connected with the base terminal of the NPN bipolar junction transistor 15. The emitter terminal of the bipolar junction transistor 12 is tied to a supply voltage source VCC and the emitter terminal of the bipolar junction transistor 15 is tied to a ground reference. Further, the collector terminal of the PNP bipolar junction transistor 12 is electrically connected with the collector terminal of the NPN bipolar junction transistor 15 and form an SOI lateral bipolar inverter device 10 output.
FIG. 2 shows a pair of complementary bipolar inverters cross-coupled to form a bistable memory element (cell) 55 with relatively large noise margin. In the cross-coupled implementation shown, the memory element 55 includes a first set of lateral bipolar transistors 32 fabricated on the SOI substrate and a second set of lateral bipolar transistors 42 fabricated on the SOI substrate. As discussed above, the first set of lateral bipolar transistors 32 is configured to form a first inverter device 50 and the second set of lateral bipolar transistors 42 is configured to form a second inverter 60. Furthermore, the first inverter 50 is cross-coupled to the second inverter 60 such that a first input terminal 51 to the first inverter 50 is electrically coupled to a second output terminal 62 of the second inverter 60, and the second input terminal 61 of the second inverter 60 is electrically coupled to the output terminal 52 of the first inverter 50. In this configuration, the cross-coupled inverters act as a memory element for storing a logic state, e.g., a logic “1” or logic “0”.
As shown in FIG. 3, a memory cell 55′ includes the memory element 55 of FIG. 2 and further includes: first access transistor 74 controlling electrical impedance from the first inverter 50 to a bit line true (BLT) conductor 75, and second access transistor 76 controlling electrical impedance from the second inverter 60 to bit line complement (BLC) conductor 85. In one embodiment, the first and second access transistors 74 and 76 are field effect transistors (FETs). For example, the first and second access transistors 74 and 76 may be n-channel FETs or p-channel FETs. Additionally, each of the first and second access transistors 74 and 76 include a gate terminal coupled to a word line 95. Such a configuration is taught and described in U.S. Pat. No. 8,526,220.
In the circuit 55′ of FIG. 3, in a standby mode, the voltage at VDD is lowered (e.g., 0.5 Volts) to take advantage of the memory element's noise margin characteristics. Furthermore, a voltage VEE is set to 0 Volts. The wordline 95 is also set to 0 Volts, thereby turning off the access transistors 74 and 76.
In the prior art circuit of FIG. 3, during a memory write operation, VEE is set to 0 Volts. BLT 75 voltage is set to the desired binary value to be stored. Likewise, BLC 85 is set to the complement of the desired binary value to be stored. The wordline 95 is then raised to VDD so that the memory cell 55 is overwritten with the desired binary value.
During a memory read operation, VEE is pulled negative to avoid read disturb. In other words, the inverter circuits 50 and 60 must carry enough current to supply the FET current to maintain memory cell stability. In general, the larger the voltage difference between VCC and VEE, the more current the bipolar inventors can supply. The word line 95 corresponding to the memory cell 55′ is then set so that the access transistors 74 and 76 are activated. Sense amplifiers (not shown) coupled to the memory cell's BLT 75 and BLC 85 lines are then used to detect the logic value stored in the memory cell 55′.
The memory cell 55′ according to prior art implementation of FIG. 3 requires a BiCMOS process, i.e. a manufacturing process that integrates both SOI lateral bipolar inverters and MOSFETs on the same substrate, to build the SRAM which, as known, is not cost-effective.